1. Field of the Invention
The present invention relates generally to a cell receiver system with source clock recovery, and more particularly to an ATM (Asynchronous Transfer Mode) cell receiver system for use in the transmission of information at a fixed rate in an ATM scheme.
2. Description of the Related Art
In an ATM transmission/switching scheme which transmits and switches information in the form of a fixed length packet called a cell, cell loss (lost cells) and bit errors may occur in the course of transmission. For this reason, an error correcting method which combines octet interleave and error correction may be employed for recovering original data from received data which suffers from cell loss and bit errors. In addition, a source clock recovery method may be employed for recovering a source clock at a rate corresponding to a fixed rate information generated on the transmission side (ITU-T (International Telecommunication Union--Telecommunication Standardization Sector) Recommendation I.363).
FIG. 1 illustrates the structure of data in a cell which is handled by a cell receiver system used in an ATM transmission/switching scheme of the type mentioned above. A header 31 (including data of fine octets) contains information indicative of the destination of the cell or the like which, however, is not used in the cell receiver system itself. An AAL (ATM Adaptation Layer) header 32 (including data of one octet) contains information used for detecting cell loss on the reception side. Specifically, a serial number is inserted into the AAL header 32 of the cells on the transmission side. A payload 33 (including data of 47 octets) contains information to be transmitted.
Next, an error correcting method employing a combination of octet interleave and error correction will be explained with reference to FIGS. 2A-2E and 3A-3E.
On the cell transmission side, a 4-octet error correcting code is added to every 124 octets of information received from a terminal to assemble a block having a length of 128 octets, as illustrated in FIGS. 2A and 2B. Data constituting the block having a length of 128 octets are sequentially written into an interleave memory 41 in the transmission side having a size of 128 octets by 47 octets, as illustrated in FIG. 2C, in the x-direction. When the data have been thus written into the interleave memory 41 on the transmission side, the written data are sequentially read therefrom in the y-direction. In this way, octet-interleaved data each having 47 octets are created as illustrated in FIG. 2D. The 47-octet data is inserted into the payload 33 illustrated in FIG. 1. Subsequently, the header 31 and the AAL header 32 are added to the payload 33 to assemble a cell which is transmitted from the cell transmission side to the cell reception side.
On the cell reception side, it is confirmed whether or not any serial number inserted in the AAL header 32 in received cells is missing. If it is confirmed that no serial number is missing, 47-octet data inserted in the payloads 33 of the received cells are sequentially written into an interleave memory 51 on the reception side having a size of 128 octets by 47 octets, as illustrated in FIG. 3B, in the y-direction. On the other hand, if it is confirmed that any serial number is missing, 47-octet data inserted in the payloads 33 of the received cells are sequentially written into the interleave memory 51 on the reception side in the y-direction with a region of the memory 51 reserved for the number of lost (missing) cells, as illustrated in FIG. 3C. When the data have been thus written into the interleave memory 51 on the reception side, the written data are sequentially read therefrom in the x-direction. In this way, data each having 128 octets are created as illustrated in FIGS. 3D and 3E. In FIGS. 3C and 3E, meshed portions represent data lost due to the cell loss. Also, the last four octets of each 128-octet data, indicated by hatching, represent the error correcting code added thereto on the transmission side. This error correcting code is used to recover data lost due to the cell loss.
Assuming, for example, that one cell is lost during transmission, data are written into the interleave memory 51 on the reception side with a region corresponding to one column being reserved in the y-direction. Thus, one octet of data is lost in each of 128-octet data sequentially read from the interleave memory 51 on the reception side in the x-direction. The lost one octet of data is recovered using the error correcting code located in the last four octets of the 128-octet data.
Next, how a source clock is recovered according to an adaptive clock scheme will be explained with reference to FIG. 4. The source clock recovery according to the adaptive clock scheme controls a clock for reading data from a buffer 61 (read clock) with a phase locked loop (PLL) 62 such that data inserted in the payloads 33 of received cells are once written into the buffer 61 while the buffer 61 is used at a constant level. More specifically, when fixed rate information is assembled into cells for transmission on the transmission side, cells are transmitted at regular intervals, so that the rate of the fixed rate information (rate of a source clock) can be recovered on the reception side by controlling the use level of the buffer 61 (i.e. the amount of data stored in the buffer 61) to be constant.
A cell receiver system of the present invention relates to a system which receives cells assembled from fixed rate information and recovers the original fixed rate information, and more particularly, performs the error correction processing and the source clock recovery processing according to the adaptive clock scheme (for example, H. Uematsu et al., "CLAD Implementation and Experimental Results in ATM networks", Institute of Electronics, Information and Communication Engineers Report, B-I, Vol. J77-B-I, No. 11, pp. 684-694, Nov. 1994).
Next, a first prior art example of the cell receiver system of the type mentioned above will be described with reference to FIG. 5. A cell disassemble means 71 in the illustrated cell receiver system processes an AAL header 32 of each of received cells to separate a payload 33 from the cell. A first buffer 72 stores data inserted in the payloads 33 separated by the cell disassemble means 71 to absorb variations in interval between cells due to delay. An interleave memory 73 stores data outputted from the first buffer 72 for octet interleave processing. An error correcting means 74 processes an error correcting code included in data outputted from the interleave memory 73 to correct possible errors in the data outputted from the interleave memory 73. A second buffer 75 stores data outputted from the error correcting means 74 except for the error correcting code for converting the received data to fixed rate data (fixed rate information). A PLL 76 recovers a source clock based on a use level of the first buffer 72. A counter means 77 generates a read clock for the first buffer 72, an operating clock for the interleave memory 73, an operating clock for the error correcting means 74, and a write clock for the second buffer 75, respectively, from the source clock recovered by the PLL 76.
In this cell receiver system, the cell disassemble means 71, after confirming a serial number inserted in the AAL header 32 of each of received cells, separates the payload 33 from the header 31 and the AAL header 32. Data inserted in the separated payload 33 is written into the first buffer 72. The data written into the first buffer 72 is sequentially read therefrom in response to the read clock from the counter means 77 and written into the interleave memory 73 in the y-direction. The data written into the interleave memory 73 is sequentially read therefrom in the x-direction, such that every 128 octets of data are sent to the error correcting means 74. The error correcting means 74 uses the error correcting code included in the 128-octet data sent thereto from the interleave memory 73 to recover data lost due to cell loss and transmission errors. The error correcting means 74 outputs 124-octets of the 128-octet data from which 4-octets of the error correcting code have been removed, and the 124-octet data are written into the second buffer 75. The 124-octet data written into the second buffer 75 are read by the source clock recovered by the PLL 76 to be recovered to the original fixed rate information which is outputted to a terminal.
The PLL 76 recovers the source clock generated on the transmission side based on the use level of the first buffer 72 according to the adaptive clock scheme. However, if an error correcting code or the like is transmitted together with information to be recovered, as is the case of applying an error correcting method to the data transmission, data must be read from the first buffer 72 at a rate higher by a fraction corresponding to the error correcting code than the rate of the recovered source clock. For this reason, the cell receiver system employs the counter means 77 for generating a clock at a rate higher than the source clock recovered by the PLL 76 for allowing for the error correcting code (i.e., source clock.times.128/124). Assuming, for example, that the source clock on the transmission side is at 1,544 kHz, the PLL 76 recovers the source clock at 1,544 kHz, and the counter means 77 generates a clock at a rate higher than the source clock by a fraction corresponding to the error correcting code (at 1,544.times.128/124 kHz). It should be noted that the counter means 77 may be implemented by a PLL.
Next, a second prior art example of the cell receiver system of the type mentioned above will be described with reference to FIG. 6. A cell disassemble means 81 in the illustrated cell receiver system processes an AAL header 32 in each of the received cells to separate a payload 33 from the cell. A first buffer 82 stores data inserted in the payloads 33 separated by the cell disassemble means 81 to absorb variations in interval between cells due to delay. An interleave memory 83 stores data outputted from the first buffer 82 to perform octet-interleave processing. An error correcting means 84 processes an error correcting code included in data outputted from the interleave memory 73 to correct possible errors in the data outputted from the interleave memory 73. A second buffer 85 stores data outputted from the error correcting means 74, except for the error correcting code, for converting the received data to fixed rate data (fixed rate information). A first PLL 86 generates a read clock for the first buffer 82, an operating clock for the interleave memory 83, an operating clock for the error correcting means 84, and a write clock for the second buffer 85, respectively. A second PLL 87 recovers a source clock based on a use level of the second buffer 85.
In the cell receiver system mentioned above, the cell disassemble means 81, after confirming a serial number inserted in the AAL header 32 of each of received cells, separates the payload 33 from the header 31 and the AAL header 32. Data inserted in the separated payload 33 is written into the first buffer 82. The data written into the first buffer 82 is sequentially read therefrom in response to the read clock from the first PLL 86 to absorb variations in interval between cells due to delay, and then written into the interleave memory 83 in the y-direction. The data written into the interleave memory 83 is sequentially read therefrom in the x-direction, such that every 128 octets of the data are sent to the error correcting means 84. The error correcting means 84 uses the error correcting code included in the 128-octet data sent thereto from the interleave memory 83 to recover data lost due to cell loss and transmission errors. The error correcting means 84 outputs 124-octets of the 128-octet data from which the 4-octets of the error correcting code have been removed, and the 124-octet data are written into the second buffer 85. The 124-octet data written into the second buffer 85 are read at the rate of the source clock recovered by the second PLL 87 to be recovered to the original fixed rate information which is outputted to a terminal.
If an error correcting code or the like is transmitted together with information to be recovered, as is the case of applying an error correcting method to the data transmission, data must be read from the first buffer 82 at a rate higher by a fraction corresponding to the error correcting code than the rate of the recovered source clock. For this reason, the first PLL 86 generates a clock at a rate higher than the source clock for allowing for the error correcting code based on the use level of the first buffer 82 according to the adaptive clock scheme, such that data is read from the first buffer 82 in response to the thus recovered clock. The second PLL 87 in turn recovers the source clock based on the use level of the second buffer 85. Assuming, for example, that the source clock at the transmission side is at 1,544 kHz, the first PLL 86 recovers a clock at a rate higher than the source clock by a fraction corresponding to the error correcting code (at 1,544.times.128/124 kHz), and the second PLL 87 recovers a clock at 1,544 kHz which is equal to the source clock.
As described above, the conventional cell receiver systems may also receive cells assembled from fixed rate information and perform the error correction processing and the processing for recovering the source clock according to the adaptive clock scheme to recover the original fixed rate information.
However, the cell receiver system of the first prior art example has a problem that if cell loss occurs in the course of transmission, the use level of the first buffer 72, employed as the basis for recovering the source clock, becomes lower so that the frequency of a recovered source clock is temporarily lowered to cause a larger amount of jitter in the source clock.
On the other hand, the cell receiver system of the second prior art example has a problem that the need for the first PLL 86 for controlling data read from the first buffer 82 for absorbing variations in interval between delays due to delay and the second PLL 87 for recovering the source clock results in increasing its hardware scale.